The present invention relates to the manufacturing engineering of a semiconductor device, particularly relates to a bonding technique for bonding an inner lead laid on a carrier to an electrode pad formed on a semiconductor chip (hereinafter called chip) and, for example, relates to a bonding technique effective when utilized for a method of manufacturing a semiconductor integrated circuit (hereinafter called IC) provided with a chip-sized package or a chip scale package (hereinafter called CSP) in size equal to or approximately equal to the size of a chip.
As electronic equipment using ICs are miniaturized and thinned, the reduction of an IC package is desired. Various CSPs are developed to meet the above demand and, a micro ball grid array package (hereinafter called xcexcBGA) constituted as follows is one example. That is, a tape carrier is mechanically connected on the main surface on the side of an electrode pad of a chip via an insulating film, each inner lead laid on the tape carrier is bonded to each electrode pad of the chip and a bump as each external terminal is soldered to each outer lead and protruded.
For a method of bonding an inner lead in xcexcBGA, there is a single point bonding method (hereinafter called only bonding method) of successively welding multiple inner leads one at a time on each electrode pad arranged on the overall chip with pressure by a bonding tool.
CSP is described on pages 112 and 113 of a monthly, xe2x80x9cSemiconductor Worldxe2x80x9d published in May, 1995 by Press Journal.
For an example describing a method of bonding a memory chip to a TAB package in which when a memory chip is mounted in a tape automated bonding (TAB) type package according to a lead on chip method based upon a film carrier, no deterioration in the strength of bonding caused by the dislocation of bonding occurs, further forming of a metallic mold and others are not required and the cost is low, there is Japanese Patent Application Laid-Open No. Hei 6-13428. In the above bonding method, after an inner lead is bend and transformed by a bonding tool before bonding, the inner lead is pressurized by the bonding tool and bonded to an electrode pad of a chip.
However, it is clarified by the inventor that in the above bonding method, there is a problem that the center line of an inner lead cannot be recognized by an image recognition device because an electrode pad is located right under an inner lead.
Also, it is clarified by the inventor that in the above bonding method, there is a problem that the looped form of each inner lead after bonding is different because an error occurs in an interval between an inner lead and an electrode pad successively bonded by a bonding tool when a chip mechanically connected to an insulating film is tilted.
Further, it is clarified by the inventor that in the above bonding method, there is a problem that as an inner lead horizontally extended is bent and transformed by a bonding tool, the inner lead is distorted, stress is left in the inner lead after inner lead bonding and as a result, when stress generated by difference in the coefficient of thermal expansion (hereinafter called thermal stress) operates in a temperature cycle acceleration test and others, a part in which stress is left of the inner lead is cracked.
An object of the present invention is to provide bonding technique in which the center line of an inner lead can be recognized independent of an electrode pad.
Another object of the present invention is to provide bonding technique in which a looped form after bonding can be stabilized.
Another object of the present invention is to provide bonding technique in which stress can be prevented from being left in an inner lead after inner lead bonding.
Another object of the present invention is to provide bonding technique in which manufacturing based upon a tape can be realized by securing alignment based upon a tape.
The above objects, other objects, and the new characteristics of the present invention will be clarified from the description in this specification and attached drawings.
The outline of typical ones of inventions disclosed in the present invention will be described below.
That is, a method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is mechanically connected to a carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the semiconductor chip is bonded to the above each inner lead is characterized in that when the above inner lead is bonded to the above electrode pad, the position of the inner lead is observed individually or collectively and the inner lead is transformed by a bonding tool and bonded to the electrode pad based upon the result of the observation.
As an inner lead is transformed by a bonding tool based upon the observation of the position of the inner lead according to the above means, the inner lead can be precisely bonded to an electrode pad.
For the outline of the other invention, in a method of manufacturing xcexcBGAxc2x7IC in which to stabilize the form of a letter S of an inner lead after bonding, a chip is fixed to a tape carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the chip is bonded to each inner lead, when an inner lead is bonded to an electrode pad, first, a chip is supplied in a fixed position for a bonding tool using a sprocket hole of a tape carrier. Next, the respective positions of the inner lead and the electrode are recognized using a feature lead and the electrode pad. Afterward, after the center line of the inner lead is recognized, the inner lead is touched to the chip by the bonding tool, pressed in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
The other outline of typical ones of inventions disclosed in the present invention will be described below.
1. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and after each electrode pad of the above semiconductor chip is aligned with each inner lead, each inner lead is bonded to each electrode pad of the semiconductor chip by a bonding tool and which is characterized by being provided with an image capturing process for capturing an image of the above inner lead having the above electrode pad as a background, an inner lead recognizing measuring line setting process for setting at least one image scanning line including the above electrode pad and at least one image scanning line on each side of the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring process for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming process for adding luminance on the above each inner lead recognizing measuring line every same point and forming an added luminance distribution waveform, and a judging process for setting a threshold value for the above added luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line of the above inner lead.
2. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and after each electrode pad of the above semiconductor chip is aligned with each inner lead, each inner lead is bonded to each electrode pad of the semiconductor chip by a bonding tool and which is characterized by being provided with an image capturing process for capturing an image of the above inner lead having the above electrode pad as a background, an inner lead recognizing measuring line setting process for setting at least one image scanning line including the above electrode pad and at least one image scanning line on each side of the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring process for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming process for setting a threshold value every the above each inner lead recognizing measuring line and forming each threshold value exceeding luminance distribution waveform, and a judging process for adding the above each threshold value exceeding luminance distribution waveform every same point, forming an added threshold value exceeding luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line of the above inner lead.
3. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and after each electrode pad of the above semiconductor chip is aligned with each inner lead, each inner lead is bonded to each electrode pad of the semiconductor chip by a bonding tool and which is characterized by being provided with an image capturing process for capturing an image corresponding to the above inner lead and the above electrode pad from the lateral direction of the above carrier and semiconductor chip, an inner lead recognizing measuring line setting process for setting at least one image scanning line corresponding to the above electrode pad and at least one image scanning line on each side of the image corresponding to the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring process for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming process for adding luminance on the above each inner lead recognizing measuring line every same point and forming an added luminance distribution waveform, and a judging process for setting a threshold value for the above added luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line in thickness of the above inner lead.
4. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and after each electrode pad of the above semiconductor chip is aligned with each inner lead, each inner lead is bonded to each electrode pad of the semiconductor chip by a bonding tool and which is characterized by being provided with an image capturing process for capturing an image corresponding to the above inner lead and the above electrode pad from the lateral direction of the above carrier and semiconductor chip, an inner lead recognizing measuring line setting process for setting at least one image scanning line corresponding to the above electrode pad and at least one image scanning line on each side of the image corresponding to the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring process for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming process for setting a threshold value every the above each inner lead recognizing measuring line and forming each threshold value exceeding luminance distribution waveform, and a judging process for adding the above each threshold value exceeding luminance distribution waveform every same point, forming an added threshold value exceeding luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line in thickness of the above inner lead.
5. A bonding machine by the bonding tool of which each inner lead aligned with each electrode pad is bonded to each electrode pad of a semiconductor chip mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and which is characterized by being provided with an image capturing device for capturing an image of the above inner lead having the above electrode pad as a background, an inner lead recognizing measuring line setting section for setting at least one image scanning line including the above electrode pad and at least one image scanning line on each side of the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring section for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming section for adding luminance on the above each inner lead recognizing measuring line every same point and forming an added luminance distribution waveform, and a judging process for setting a threshold value for the above added luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line of the above inner lead.
6. A bonding machine by the bonding tool of which each inner lead aligned with each electrode pad is bonded to each electrode pad of a semiconductor chip mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and which is characterized by being provided with an image capturing device for capturing an image corresponding to the above inner lead and the above electrode pad from the lateral direction of the above carrier and semiconductor chip, an inner lead recognizing measuring line setting section for setting at least one image scanning line corresponding to the above electrode pad and at least one image scanning line on each side of the image corresponding to the above electrode pad as each inner lead recognizing measuring line out of image scanning lines respectively perpendicular to the inner lead in the above captured image, a luminance measuring section for measuring luminance at each point on each scanning line every the above each inner lead recognizing measuring line, a forming section for adding luminance on the above each inner lead recognizing measuring line every same point and forming an added luminance distribution waveform, and a judging section for setting a threshold value for the above added luminance distribution waveform, calculating the center of gravity in an area equal to or larger than the threshold value and judging the center line in thickness of the above inner lead.
7. A bonding method in which a semiconductor chip is mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and each inner lead is bonded to each electrode pad of the above semiconductor chip by a bonding tool and which is characterized in that before the above each inner lead is bonded to each electrode pad of the above semiconductor chip by a bonding tool, a height from the surface including the above group of electrode pads of the semiconductor chip to the above bonding tool is measured and bonding by the bonding tool is executed based upon the measured height.
8. A bonding method according to Paragraph 7 characterized in that the above measurement of the height is executed by touching the above bonding tool to the surface including the above group of electrode pads of the above semiconductor chip via the above inner lead.
9. A bonding method according to Paragraph 7 characterized in that the above measurement of the height is executed by touching the above bonding tool to at least three points on the surface including the above group of electrode pads of the above semiconductor chip and acquiring the degree of parallelization of the above semiconductor chip.
10. A bonding method according to Paragraph 7 characterized in that the measurement of the height of the above semiconductor chip is executed by detecting the surface including the above group of electrode pads of the semiconductor chip by a non-contact sensor.
11. A bonding machine by the bonding tool of which each inner lead is bonded to each electrode pad of a semiconductor chip mechanically connected to a carrier on one main surface of which a group of inner leads are laid via an insulating film and which is characterized in that before the above each inner lead is bonded to each electrode pad of the above semiconductor chip by the bonding tool, a height from the surface including the above group of electrode pads of the semiconductor chip to the above bonding tool is measured and bonding by the bonding tool is executed based upon the measured height.
12. A bonding machine according to Paragraph 11 characterized in that the above height is measured by touching the above bonding tool to the surface including the above group of electrode pads of the above semiconductor chip via each inner lead.
13. A bonding machine according to Paragraph 11 characterized in that the above height is measured by touching the above bonding tool to at least three points on the surface including the above group of electrode pads of the above semiconductor chip and acquiring the degree of parallelization of the semiconductor chip.
14. A bonding machine according to Paragraph 11 characterized in that the height of the above semiconductor chip is measured by detecting the surface including the above group of electrode pads of the above semiconductor chip by a non-contact sensor.
15. A method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is mechanically connected to a carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the semiconductor chip is bonded to each inner lead and which is characterized in that when the above inner lead is bonded to the above electrode pad, the position of the inner lead is observed individually or collectively, the inner lead is transformed by a bonding tool based upon the result of the observation and bonded to the electrode pad.
16. A method of manufacturing a semiconductor integrated circuit according to Paragraph 15 characterized by being provided with a connecting process for mechanically connecting the above semiconductor chip to the above carrier via the above insulating film and a bonding process for observing the position of the above inner lead individually or collectively, transforming the inner lead by the above bonding tool based upon the result of the observation and bonding the inner lead to the above electrode pad.
17. A method of manufacturing a semiconductor integrated circuit according to Paragraph 15 characterized in that before the above inner lead is bonded to the above electrode pad, a regular part regularly arranged on the above carrier is measured and the above semiconductor chip and the above bonding tool are aligned based upon the measurement.
18. A method of manufacturing a semiconductor integrated circuit according to Paragraph 15 characterized in that a feature lead arranged beforehand on the above carrier and a feature pad arranged beforehand on the above semiconductor chip are measured and the respective positions of the above inner lead and the semiconductor chip are recognized based upon the measurement.
19. A method of manufacturing a semiconductor integrated circuit according to Paragraph 15 characterized in that the image of the above inner lead is captured and the position of the above inner lead is measured based upon the captured image.
20. A bonding machine used for a method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is mechanically connected to a carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the semiconductor chip is bonded to above each inner lead and which is characterized in that when the above inner lead is bonded to above electrode pad, the position of the inner lead is observed individually or collectively, the inner lead is transformed by a bonding tool based upon the result of the observation and bonded to the electrode pad.
21. A bonding machine according to Paragraph 20 characterized by being provided with an observation device for observing the position of the above inner lead individually or collectively and a controller for transforming the inner lead by the above bonding tool based upon the result of the observation and bonding it to the above electrode pad.
22. A bonding machine according to Paragraph 20 characterized by being provided with an observation device for observing a regular part regularly arranged on the above carrier before the above inner lead is bonded to the above electrode pad and a controller for aligning the above semiconductor chip and the above bonding tool based upon the observation.
23. A bonding machine according to Paragraph 20 characterized by being provided with an observation device for observing a feature lead beforehand arranged on the above carrier and a feature pad beforehand arranged on the above semiconductor chip and a controller for recognizing the respective positions of the above inner lead and the semiconductor chip based upon the observation.
24. A bonding machine according to Paragraph 20 characterized by being provided with an image capturing device for capturing the image of the above inner lead and a controller for observing the position of the inner lead based upon the captured image.
25. A method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is mechanically connected to a carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the semiconductor chip is bonded to the above each inner lead and which is characterized in that in the above bonding, a part of the above inner lead is bent by a bonding tool, pressed upon the above electrode pad and bonded to it.
26. A method of manufacturing a semiconductor integrated circuit according to Paragraph 25 characterized in that after a part of the above inner lead is touched onto the above semiconductor chip by the above bonding tool, the bonding tool is horizontally moved and the inner lead is bent in the form of a letter S.
27. A method of manufacturing a semiconductor integrated circuit according to Paragraph 26 characterized in that after the above bonding tool by which a part of the above inner lead is touched onto the above semiconductor chip is lifted, it is horizontally moved.
28. A method of manufacturing a semiconductor integrated circuit according to Paragraph 27 characterized in that after the above bonding tool by which a part of the above inner lead is touched onto the above semiconductor chip is lifted, the bonding tool is horizontally moved across the bonded part of the above electrode pad in the direction of the base of the inner lead and further, returned to the bonded part.
29. A method of manufacturing a semiconductor integrated circuit according to Paragraph 25 characterized in that after a part of the above inner lead is struck and cut by the above bonding tool, one cut piece is bent by the bonding tool and bonded to the above electrode pad.
30. A method of manufacturing a semiconductor integrated circuit according to Paragraph 20 characterized in that the end of the above inner lead is touched onto the above semiconductor chip by the above bonding tool.
31. A method of manufacturing a semiconductor integrated circuit according to Paragraph 25 characterized in that after a part of the above inner lead is moved in the direction of the above semiconductor chip by the above bonding tool, the bonding tool is horizontally moved and the inner lead is bent in the form of a letter S.
32. A method of manufacturing a semiconductor integrated circuit according to Paragraph 31 characterized in that after the above bonding tool by which a part of the above inner lead is moved in the direction of the above semiconductor chip is lifted, it is horizontally moved across the bonded part of the above electrode pad in the direction of the base of the inner lead and further, returned to the bonded part.
33. A bonding machine used for a method of manufacturing a semiconductor integrated circuit in which a semiconductor chip is mechanically connected to a carrier on one main surface of which plural inner leads are laid via an insulating film and each electrode pad of the semiconductor chip is bonded to the above each inner lead and which is characterized in that in the above bonding, a part of the above inner lead is bent by a bonding tool, pressed upon the above electrode pad and bonded.
34. A bonding machine according to Paragraph 33 characterized in that after a part of the above inner lead is touched onto the above semiconductor chip by the above bonding tool, the bonding tool is horizontally moved and the inner lead is transformed in the form of a letter S.
35. A method of manufacturing a semiconductor integrated circuit including the following processes:
(1) a process for supplying a chip-lead complex tape in which multiple semiconductor integrated circuit chips are fixed on a carrier tape provided with a wiring pattern including multiple inner leads to a lead bonding machine,
(2) a process for optically observing one unit area including one chip of the above multiple chips on the above supplied chip-lead complex tape in the above lead bonding machine,
(3) a process for correcting positional relationship between the above lead in a plane parallel to a first main surface of the above chip and the above pad based upon the result of the above observation in the above lead bonding machine by transforming an inner lead part to be connected to a bonding pad on the first main surface of the above one chip and projected from the surface of the above carrier tape, and
(4) a process for connecting the above lead and pad by a bonding tool after the above lead is corrected in the above lead bonding machine.
36. A method of manufacturing a semiconductor integrated circuit according to Paragraph 35 characterized in that the above lead is transformed by the above bonding tool.
37. A method of manufacturing a semiconductor integrated circuit according to Paragraph 36 characterized in that the bonding of the above lead is executed for every lead by the above bonding tool.
38. A method of manufacturing a semiconductor integrated circuit according to Paragraph 37 characterized in that a unit area on the above chip-lead complex tape corresponds to one unit or plural units of a chip-sized package.
39. A method of manufacturing a semiconductor integrated circuit consisting of the following processes:
(1) a process for supplying a chip-lead complex tape in which multiple semiconductor integrated circuit chips are fixed on a carrier tape provided with a wiring pattern including multiple inner leads to a lead bonding machine,
(2) a process for detecting relative positional relationship among the above lead bonding machine, the above pad and lead in the lead bonding machine by optically observing one unit area including one chip of the above multiple chips on the above supplied chip-lead complex tape,
(3) a process for correcting relative positional relationship between the above lead to be connected to a bonding pad on a first main surface of the above one chip in a plane parallel to the first main surface of the above chip and the above pad based upon the result of the above detection in the above lead bonding machine, and
(4) a process for connecting the above lead and pad by a bonding tool after the above correction in the above lead bonding machine.
40. A method of manufacturing a semiconductor integrated circuit according to Paragraph 39 characterized in that the bonding of the above lead is executed for every lead by the above bonding tool.
41. A method of manufacturing a semiconductor integrated circuit according to Paragraph 40 characterized in that a unit area on the above chip-lead complex tape corresponds to one unit or plural units of a chip-sized package.
42. A method of manufacturing a semiconductor integrated circuit consisting of the following processes:
(1) a process for supplying a chip-lead complex tape in which multiple semiconductor integrated circuit chips are fixed on a carrier tape provided with a wiring pattern including multiple inner leads to a lead bonding machine,
(2) a process for moving one unit area including one chip of the above multiple chips on the above supplied chip-lead complex tape to a position in which bonding is executed in the above lead bonding machine,
(3) a process for pushing down the end of an inner lead or the vicinity after being moved from on the above carrier tape moved to a bonding position in the above unit area to over the corresponding pad of a chip in the same area by a bonding tool in the above lead bonding machine,
(4) a process for forming the above inner lead by pushing the above pushed-down inner lead in the direction of the base of the inner lead across over the above pad area by the above bonding tool and transforming the above inner lead in the above lead bonding machine, and
(5) a process for bonding the above lead and pad by pressing the above formed inner lead upon the above pad by the above bonding tool.
43. A method of manufacturing a semiconductor integrated circuit according to Paragraph 42 characterized in that the above process for pushing down is continued until the above bonding tool reaches the surface of the above chip via the above inner lead.
44. A method-of manufacturing a semiconductor integrated circuit according to Paragraph 43 characterized in that the bonding of the above lead is executed for every lead by the above bonding tool.
45. A method of manufacturing a semiconductor integrated circuit according to Paragraph 44 characterized in that a unit area on the above chip-lead complex tape corresponds to on unit or plural units of a chip-sized package.
46. A method of manufacturing a semiconductor integrated circuit consisting of the following processes:
(1) a process for supplying a chip-lead complex tape in which multiple semiconductor integrated circuit chips are fixed on a carrier tape provided with wiring including an inner lead part with the above chip-lead complex tape wound on a loading reel,
(2) a process for carrying and supplying the above each lead and each bonding pad of the above chip to a part for bonding using a friction roller by successively unwinding the above chip-lead complex tape wound on the above loading reel, and
(3) a process for winding the above chip-lead complex tape on an unloading reel after bonding is finished.
47. A method of manufacturing a semiconductor integrated circuit according to Paragraph 46 characterized in that the carriage of the above chip-lead complex tape is controlled by optically detecting an opening provided periodically in the direction of the length of a carrier tape.
48. A method of manufacturing a semiconductor integrated circuit consisting of the following processes:
(1) a process for supplying a chip-lead complex tape in which multiple semiconductor integrated circuit chips are fixed on a carrier tape provided with a wiring pattern including multiple inner leads to a lead bonding machine,
(2) a process for moving one unit area including one chip of the above multiple chips on the above supplied chip-lead complex tape to a position for executing bonding in the above lead bonding machine,
(3) a process for pushing down the vicinity of the end of an inner lead which is set so that the end of the inner lead is located in an opening through the opening of a tape over the corresponding pad of a chip in the above unit area from on the above carrier tape moved to a bonding position in the same area, that is, a lead on the reverse side to the above inner lead in a part to be cut which is formed so that it is weaker than the other part by a bonding tool in the above lead bonding machine,
(4) a process for forming the above inner lead by transforming the inner lead cut as a result of pushing down by the above bonding tool in the above lead bonding machine, and
(5) a process for bonding the above lead and pad by pressing the above formed inner lead upon the above pad by the above bonding tool.
49. A method of manufacturing a semiconductor integrated circuit including the following processes:
(1) a process for supplying a chip-lead complex tape in which multiple semiconductor integrated circuit chips are fixed on a carrier tape provided with a wiring pattern including multiple inner leads to a lead bonding machine,
(2) a process for moving one unit area including one chip of the above multiple chips on the above supplied chip-lead complex tape to a position for executing bonding in the above lead bonding machine,
(3) a process for diagonally pushing down the end of an inner lead or the vicinity which is set so that the end of the inner lead is located in an opening through the opening of a tape over the corresponding pad of a chip in the above unit area from on the above carrier tape moved to a bonding position in the same area from the reverse side to the above inner lead in a part to be cut which is formed so that it is weaker than the other part to the side of the base of the above inner lead by a bonding tool in the above lead bonding machine,
(4) a process for forming the above inner lead by transforming the inner lead cut as a result of pushing down by the above bonding tool in the above lead bonding machine, and
(5) a process for bonding the above lead and pad by pressing the above formed inner lead upon the above pad by the above bonding tool.
50. A lead bonding machine characterized in that after a chip-lead complex tape in which a semiconductor integrated circuit chip is fixed on a carrier tape is supplied with the above tape wound on a loading reel, carried by a friction roller and a lead is bonded to a bonding pad on the above semiconductor integrated circuit chip, the above tape is wound on an unloading reel.
51. A lead bonding machine according to Paragraph 50 characterized in that if correction is required, the bonding of the above lead is executed after positional relationship between the above lead and the corresponding bonding pad is corrected by transforming an inner lead part of the lead.
52. A lead bonding machine according to Paragraph 51 characterized in that the correction by transformation of the above lead is executed if necessary based upon the result of optically observing positional relationship between a lead and a bonding pad.
53. A lead bonding machine according to Paragraph 52 characterized in that the bonding of the above lead is executed for every lead by a bonding tool.
54. A lead bonding machine according to Paragraph 53 characterized in that the correction by transformation of the above lead is executed for every lead by the above bonding tool.